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never stop thinking. power management & supply data sheet, april 2001 tda 16850-2 free running and synchronized smps controller www.datasheet.co.kr datasheet pdf - http://www..net/
p-dip-8 data sheet 2 04.01 synchronized smps controller type ordering code package TDA16850-2 q67040-s4404-a p-dip-8 tda 16850-2 ac 90v - 270v standby gate gnd failure modes mains undervoltage ov erv ol tage overtemperature open loop failure undervoltage over current protection short circuit protection oscillator 20 khz / 60 khz & external synchronisation delay 70 s pwm current mode driver u sst f clock power limitation s r q s upply vcc v vreg v (*) power management internal bias power down reset power up reset undervoltage lockout 23 v 7, 5 v voltage reference 6 3 8 4 2 7 5 1 vcc sst cs op to sync vreg sst c opto r se nse r convert er dc o ut put feedback feedback (*) supply by vreg if vcc < 11v product highlights ? synchronisation range 30 khz to 130 khz maximum output power independant of frequency standby mode with reduced output voltage by factor 5 mode changing and voltage feedback through only one optocoupler off mode with power consumption less than 250 mw standby mode with power consumption less than 1w without synchronisation operation with internal oscillator 20khz/60khz different failure modes recognition with latch function minimum external circuitry typical application www.datasheet.co.kr datasheet pdf - http://www..net/
TDA16850-2 data sheet 3 04.01 table of contents 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.2 special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.3 protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.4 general remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.6 pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1 off mode / switch on process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.2 startup mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.3 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.4 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.5 power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.6 protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.7 protection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.7.1 over current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.7.2 short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.7.3 failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.7.3.1 mains undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.7.3.2 ic supply overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.7.3.3 ic overtemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.7.3.4 vreg loop failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.7.3.5 ic supplyundervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.1 vcc and vreg section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.2 opto section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.3 oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.4 pwm section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.5 current sense section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.6 soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.7 output power limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.8 gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.9 protection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.9.1 over current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.9.2 short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.9.3 failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.9.3.1 mains undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.9.3.2 ic supply overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.9.3.3 ic overtemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.9.3.4 vreg loop failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 www.datasheet.co.kr datasheet pdf - http://www..net/
TDA16850-2 data sheet 4 04.01 3.9.3.5 ic supply undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 application circuit 1. see description 5.3.1 . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 application circuit 2. see decription 5.3.2 . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 description of application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3.1 application circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3.2 application circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet 5 04.01 synchronized smps controller as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies . the information describes the type of component and shall not be considered as assured characteristics. type ordering code package TDA16850-2 q67040-s4404-a p-dip-8 tda 16850-2 1 overview 1.1 features ? controller for flyback topology ? current mode pwm with shunt resistor and spike blanking ? leading edge triggered pulse width modulation ? fast, soft switching totem pole gate drive (1 a) ? soft start management for safe start up 1.2 special features ? typical 100 a start-up supply current ? low quiescent current (5 ma) ? maximum output power independent of frequency ? 20 khz internal oscillator for start-up and standby mode ? 60 khz internal oscillator for non synchronized normal mode ? synchronization range 30 khz to 130 khz ? feedback via optocoupler in normal operation ? feedback via transformer winding in standby mode ? standby mode with reduced output voltages by factor of 5 ? off mode with power consumption less then 1 w ? mode switching and voltage feedback through only one optocoupler ? different failure modes recognition with latch function 1.3 protection features ? fast and slow peak current limitation ? mains undervoltage protection ? ic supply overvoltage ? ic supply undervoltage ? loop failure ? over temperature switch off ? over current protection ? short circuit protection 1.4 general remarks the tda 16850-2 comprises the complete control for flyback switched mode power supplies especially in crt monitors. it also performs all necessary protection functions in flyback converters. the tda 16850-2 applies to converters with input line voltages ranging from 90 v ac t o 270 v ac . the maximum duty cycle depends on frequency, line voltage and soft start management. the maximum output power therefore will be limited effectively in case of a secondary overload. all clock signals as well as the pwm voltage ramp are either synchronized by the internal oscillator or by the synchronisation signal at pin sync. the internal oscillator is activated if there is no signal at sync. an horizontal deflection signal at pin sync synchronizes the internal oscillator automatically. mode switching is done via the input current at pin opto. in the standby mode the tda 16850-2 gets its supply from pin vreg. the voltage at vreg is then also the feedback voltage. the tda 16850-2 will switch off the power supply and enter the off mode when the optocoupler current is completely turned off. it can restart from a short optocoupler current pulse, which can be derived from a vertical synchronization pulse. the tda 16850-2 operates in the normal mode if v vcc and i opto are in their nominal range. www.datasheet.co.kr datasheet pdf - http://www..net/
TDA16850-2 data sheet 6 04.01 gate gnd failure modes mains undervoltage overvoltage overtemperature open loop failure undervoltage over current protection short circuit protection oscillator 20 khz / 60 khz & external synchronisation delay 70 s pwm current mode driver u sst f clock power limitation s r q supply vcc v vreg v (*) power management internal bias power down reset power up reset undervoltage lockout 23 v 7,5 v voltage reference 6 3 8 4 2 7 5 1 vcc sst cs opto sync vreg sst c (*) supply by vreg if vcc < 11v 1.5 block diagram www.datasheet.co.kr datasheet pdf - http://www..net/
TDA16850-2 data sheet 7 04.01 1.6 pin connection and description pin name function 1 sst soft-start pin for external capacitor c sst 2 vreg supply and feedback during standby mode 3 cs current sense 4 sync synchronization input 5 gnd ground 6 gate high current totem pole output 7 vcc start up and supply during normal mode 8 opto feedback and mode switching via input current sync cs vreg sst gnd gate vcc opto 1 2 3 4 8 7 6 5 p-dip-8-4 (plastic dual in-line package) www.datasheet.co.kr datasheet pdf - http://www..net/
TDA16850-2 data sheet 8 04.01 2 functional description figure 1 flow chart of operation note: if not otherwise stated the figures shown in this section represent typical performance characteristic latch t delay = 70s v vcc < 7.5 v startup mode v vcc < v z1 i vcc = 3 m a + i opto i opto = 0 ... 2 m a (u opto = 2 v) v vreg = 11 v f gate ( no sync) = 20 khz f gate (sync) = 30 ... 130 khz standby mode v vcc < v z1 i vcc = 3 m a + i opto + i gate i opto =0,16 ... 2 m a (u opto = 2 v) v reg = 11 v f gate ( no sync) = 20 khz f gate (sync) = 30 ... 130 khz off mode v vcc < 21 v i vcc < 100 a i opto < 50 a (u opto = 0,5 v) f gate = 0 khz normal mode v vcc < v z1 i vcc = 3 m a + i opto + i gate i opto = 2 ... 6 m a (u opto = 2 v) v reg = 11 v ... 85 v f gate ( no sync) = 60 khz f gate (sync) = 30 ... 130 khz v vcc > 21 v i opto > 2ma power down mode i vcc = 3 m a + i opto + i gate i opto = 0 ... 160 ua (u opto = 2 v) f gate = 0 khz i opto > 160 a i opto < 2m a i opto < 160 a t > 10 s i opto > 50 a t i main switch "on" u cs 1.2 v u sst t t over current v cs > 1.2 v short circuit v cs > 1.5 v i opto > 2ma u cs 1.5 v u gate t t protection mode f gate = 0 khz v vcc 0 v v sst 0 v failure modes ic overtemperature t j > 150 c ic supply overvoltage v vcc > 23 v vreg loop failure v sst > 2.6v & v vreg < 3v mains undervoltage dv cs dt 70 mv 1 sec < ic supply undervoltage v vcc < 8 v www.datasheet.co.kr datasheet pdf - http://www..net/
TDA16850-2 data sheet 9 04.01 figure 2 timing diagram of operation without synchronization v opto v vcc i opto 50 a off mode startup mode 160 a 2 ma 21 v normal mode standby mode 6 ma power down mode 15 v 8 v 7.5 v protection mode off mode 0,5 v 2 v i vcc 100 a 3 ma 7 ma v gate v vreg 11 v 85 v time 9,5 v time time time time time www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet 10 04.01 TDA16850-2 (see figure 1, page4 and figure 2, page 5 ) 2.1 off mode / switch on process at first the chip is in off mode. during switch on process the supply voltage at vcc increases from 0 v to the switch on threshold of v vcc . the total current consumption of tda 16850-2 is typ.100 a in this case. when v vcc exceeds the voltage of 21 v the chip can be activated by an optocoupler current pulse higher than 50 a (typ.) and 10 s (typ.) duration. 2.2 startup mode entering startup mode the internal supply of tda 16850-2 is switched on and all blocks are operable. in the startup mode a current out of pin opto of 0 a < | i opto | < 2 ma is allowed. if there is no signal at pin sync, the tda 16850-2 generates gate pulses at a rate of 20 khz (typ.). the pulse width is first increased during a soft start and then regulated for 11 v voltage at pin vreg. 2.3 normal mode normal mode can be entered from startup mode or standby mode by increasing the opto current above 2 ma (typ.). in the normal mode the supply voltage must be 8 v < v vcc < 23 v typ. when there is no signal present at sync, gate clocks with a frequency of typical f osc = 60 khz (typ.). if there is a signal at sync of 30 khz < f osc < 130khz the internal oscillator is synchronized automatically with this signal. if the vreg voltage is higher than 11 v, the output pulse width depends on the opto current. a higher opto current means wider output pulses and a higher output power of the power supply. duty cycle minimum will be achieved at a opto current of 2 ma (typ.). 2.4 standby mode standby mode is reached from either normal mode or power down mode by adjusting the opto current within 160 a to 2 ma. voltage v vreg will then be regulated to typ. 11 v. the oscillator frequency in standby mode is typ. 20 khz. a signal at pin sync is also evaluated in standby mode and the oscillator is synchronized accordingly. standby mode can be quit to move to normal mode, power down mode, or to move to protection mode. in the standby mode the supply to the chip can be switched over from pin vcc to pin vreg. the switch is a current limiting switching transistor. it?s switched on when v vcc drops below typ. 10 v in normal mode. when v vreg is greater than v vcc the chip is now supplied via v vreg . at the same time the internal control of the duty cycle at gate is set so that there is typically a voltage of 11 v at pin vreg. at vcc there is then a voltage of typ. 9.5 v. the current at pin opto must stay between 160 a < | i opto | < 2 ma. 2.5 power down mode at power down mode gate will be disabled. the power down mode is entered when the opto input current is less than 160 a (typ.), after the ic has been in the normal mode before. 2.6 protection mode all failure modes will disable gate. this is the protection mode, which is latched and vcc and sst will be discharged by internal transistors. protection mode can only be left through the off mode if v vcc is below 7.5 v (typ.). 2.7 protection circuitry 2.7.1 over current the voltage at pin cs will be sensed by a comparator. until the voltage at pin cs is more than 1,2v (typ.) the duty cycle will be reduced by discharging pin sst by a internal transistor. 2.7.2 short circuit in case of a secondary short circuit, gate will be disabled as long as the voltage at pin cs is more than 1,5 v (typ.). 2.7.3 failure modes the error message of the failure functions are stored in a latch after a delay of typ. 70 s. gate then will be disabled. the latch is reset again when the chip is in off mode . 2.7.3.1 mains undervoltage a circuit checks the rise of the ramp singal at pin cs for minimum slew rate. 2.7.3.2 ic supply overvoltage a circuit checks the voltage at pin vcc. 2.7.3.3 ic overtemperature a thermal probe checks the temperature of the chip. 2.7.3.4 vreg loop failure a circuit checks if the voltage at vreg is below 3 v (typ.) and the voltage at pin sst have reached 2,6v (typ.). 2.7.3.5 ic supplyundervoltage a comparator checks the voltage at vcc. www.datasheet.co.kr datasheet pdf - http://www..net/
TDA16850-2 data sheet 11 04.01 3 functional block description figure 3 block diagram gate opto oscillator 20 khz & 60 khz sst 8 v 2 v & 1 r s q & r s q 2 4 7 8 11 v & 20 a 3 10 a 1.5 v comp 2 1.2 v comp 3 op 1 r3 750 op 2 comp 11 comp 4 3 v comp 10 2.6 v r1 z 1 comp 7 comp 8 t1 overtemp. detect. temp u t 1 5 vcc 6 ff 2 ff 1 1 v comp 1 u sst f clock powerlimit t 2 delay 70s 1 v t 3 t 5 t 6 1 7,5 v 7,5 v 2 v i ota 1 comp 12 z 2 11 v op 4 t 4 d1 comp 6 comp 5 gnd sync cs vreg vcc starting-up hyst. 7.5 v - 23 v voltage reference power management r9 comp 9 t 7 r2 200k c1 5pf r5 37k r4 10k r6 60k 7,5 v 2 a c2 5pf c3 0.5pf 2.11 v comp 12 3.5 v op 3 r8 35 k 7,5 v r7 40k pwm v www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet 12 04.01 TDA16850-2 3.1 vcc and vreg section the tda 16850-2 is protected against overvoltages above 23 v typ. by an internal zener diode z1 at pin vcc (see figure 4 ). figure 4 undervoltage lockout hysteresis and ze- ner diode overvoltage protection in the normal mode the chip is supplied via vcc. the nominal voltage at vcc then is typ. 15 v. the feedback path leads from a secondary voltage (e.g. 190 v) through a secondary reference element (i.e. tl 431) and the optocoupler to the feedback pin opto (see figure 19 ) . in standby mode the chip is supplied via pin vreg. pin vreg is then the feedback input at the same time. the voltage at vreg is regulated to typ. 11 v via ota1 (see figure 5 ). the intern supply voltages are then derived from the voltage at vreg via op4 , d1 and t4 figure 5 transferfunction of ota1 3.2 opto section at pin opto (see figure 6 ) the tda 16850-2 has an integrated 150 khz lowpass filter which eliminates interference spikes . figure 6 output characteristic of pin opto in normal mode pin opto is the feedback input for the tda 16850-2 via op2 (see figure 7 ). figure 7 transferfunction of op2 comp11 checks the current at pin opto. if i opto falls below 160 a gate will be disabled . 3.3 oscillator and synchronization in standby mode and in startup mode the oscillator frequency is typ. 20 khz. in normal mode the unsynchronized oscillator frequency is typ. 60 khz. if there is a signal present at sync within 30 khz to 130 khz, the oscillator switches automatically to synchronized operation. the synchronisation input is positive edge triggered. the gate output pulse begins after the rising edge of 0 1 2 3 4 5 0 2 4 6 8 1012141618202224 v v vcc ma i vcc 0,0 1,0 2,0 3,0 4,0 5,0 6,0 7,0 10,4 10,525 10,65 10,775 10,9 11,025 v v vreg v v pwm 0,0 0,5 1,0 1,5 2,0 2,5 012345678 ma i opto v v opto 0,0 1,0 2,0 3,0 4,0 5,0 6,0 7,0 012345678 ma i opto v v pwm www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet 13 04.01 TDA16850-2 the sync signal with a delay, which is 1/20 of the sync signal period (see figure 8 ). figure 8 timing diagram oscillator with synchro- nisation figure 9 timing diagram 60/20 khz switch and synchronisation if i opto falls below 2 ma the unsynchronized oscillator will switch from 60 khz to 20 khz (see figure 9 ). the sync input is protected by a zener diode z2 and a hysteresis comparator comp1 . 3.4 pwm section the pwm section is equipped with improved current mode control. the pulse width modulator of the tda 16850-2 operates at a small pulse width in voltage mode and with a larger pulse width in current mode. the gate puls depends on the sst voltage via comp4 , the opto current via comp5 and the vreg voltage via comp6 . a voltage at vreg lower than 11 v will lead to long gate pulses, as well as a high opto current. a low voltage at sst dominates over the opto and vreg conditions and sets the limit for the maximum gate pulse width. the input, which generates the longer gate pulses will dominate over the input, which would generate the shorter gate pulses (see figure 10 ). figure 10 timing diagram pwm section v comp1 v osc v gate time time time v sync time i opto 2 ma v osc v sync time time time v osc v gate v cs v rmp time time time time v pwm off v pwm on www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet 14 04.01 TDA16850-2 3.5 current sense section the voltage at the shunt resistor of the power mos is fed to op1 (see figure 11 ) via pin cs. no other external circuit is required. an internal low pass filter with an initial condition suppresses a leading spike at cs up to 150nvs typ. figure 11 transferfunction of op1 3.6 soft start on the transition from off mode to startup mode a soft start is activated. depending on the voltage at the capacitor at pin sst the increasing of the duty cycle is controlled via comp4 . 3.7 output power limiting after the end of the soft start there is a maximum voltage at the capacitor at pin sst. this voltage is a signal for the maximum possible pulse width at gate via comp4 . the maximum voltage at sst is regulated depending on the oscillator frequency. the value of the voltage is derived from the square root of the oscillator period. the energy that can be stored in the transformer is reduced in proportion to the oscillator frequency. the maximum output power is idependent from sync frequency (see figure 12 ).this reduces the danger of fire if a defect within the load circuit occurs. figure 12 voltage at softstart capacitor vs. oscil- lator frequency 3.8 gate driver gate switches from low to high first with high current and then with reduced current. this current switchover takes place at a voltage at gate of typ. 6 v (see figure 13 ). in off mode gate is safely disabled, i.e. low. in this state transients at drain with miller currents up to 20 ma can not open the power mos. figure 13 rising edge of driver output 0,00 0,50 1,00 1,50 2,00 2,50 3,00 3,50 4,00 4,50 5,00 5,50 6,00 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 v v cs v v c2 slew rate v cs = 100 mv sec 3,5 4,0 4,5 5,0 5,5 6,0 6,5 10 20 30 40 50 60 70 80 90 100 110 120 khz f gate v v sst max 0 2 4 6 8 10 12 0 50 100 150 200 250 300 350 400 time v gate ns v www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet 15 04.01 TDA16850-2 3.9 protection circuitry 3.9.1 over current a slow current limitation is realized with comp3 . if the voltage at pin cs reached 1,2v (typ.) pin sst will be discharged by t1 (see figure 14 ). figure 14 timing diagram over current function 3.9.2 short circuit by means of the fast comparator comp2 sensing at pin cs peak current limitation is realized. when being activated (v cs > 1,5v typ.) it will immediately shut down the gate (see figure 15 ). figure 15 protection function short circuit 3.9.3 failure modes the failure modes are stored in ff1 after typically 70s. gate then will be disabled und pin sst and vcc discharged by t7 and t3. ff1 is reset again when the chip is in off mode (see figure 16 ). figure 16 timing diagram failure mode 3.9.3.1 mains undervoltage comp12 checks the rise of the ramp signal at pin cs for minimum slew rate. if the ramp rise falls below a lower limit value this means the mains voltage is too low. the gate output is disabled then. 3.9.3.2 ic supply overvoltage a further comparator comp7 disables gate, if a current of more than 4 ma typ. flows over the zener diode z1 at vcc, i.e. if there is overvoltage at vcc caused by a loop fault. 3.9.3.3 ic overtemperature if in case of an error condition the tda 16850-2 is supplied over an extended period from a high feed voltage at vreg, the chip will dissipate high power. an internal overtemperature detection disables gate via ff1 if there is a thermal overload. 3.9.3.4 vreg loop failure comp9 and comp10 checks the voltage at pin vreg and sst. if v vreg is below 3 v and v sst have reached 2,6v (typ.), i.e. if there is undervoltage at pin vreg caused by a loop fault, gate will be disabled. 3.9.3.5 ic supply undervoltage comp8 checks the voltage at pin vcc. if v vcc falls below 8 v gate will be disabled. v sst v cs 1,2 v time time v rmp v gate time time v cs 1,5 v v pwm out time v failure v latch out v gate v vcc v sst 7.5 v t < 70s startup mode, normal mode, standby mode, power down mode protection mode off mode t > 70s time time time time time www.datasheet.co.kr datasheet pdf - http://www..net/
TDA16850-2 data sheet 16 04.01 4 electrical characteristics 4.1 absolute maximum ratings note: absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. to avoid destruction make sure, that for any pin except for pin gate the currents caused by transient processes stay well below 100 ma. for the same reason make sure, that any capacitor that will be connected to pin vcc and pin vreg is discharged before assembling the application circuit. t a = ? 25 to 85 c parameter symbol limit values unit remarks min. max. vcc supply voltage v vcc ? 0,3 v z1 v v z1 = 23 v typ. vreg supply voltage v vreg ? 0,3 85 v - zener current of z1 i z1 -10ma - sync current i sync -10 10 ma v sync < ? = 0,3 v or v sync > === 5 v opto voltage v opto ? 0,3 8 v - sst voltage v sst ? 0,3 8 v - cs voltage v cs ? 0,3 8 v - gate dc current i gate ? 100 100 ma - gate dc peak clamping current i gate -100ma v gate =high gate dc peak clamping current i gate ? 500 - ma v gate =low gate charge q gate ? 200 200 nc each slope, v vcc < 20 v junction temperature t j ? 25 150 c- storage temperature t s ? 65 150 c- thermal resistance r thja - 100 k/w p-dip-8 www.datasheet.co.kr datasheet pdf - http://www..net/
TDA16850-2 data sheet 17 04.01 4.2 operating range note: within the operating range the ic operates as described in the functional description. parameter symbol limit values unit remarks min. max. vcc supply voltage v vcc 0 v z1 v v z1 = zener voltage of z1 vreg voltage v vreg 085v - zener current i z1 0 4 ma limited by t j,max gate current i gate ? 11,5 a - gate dc clamping current i gate ? 200 50 ma - synchronization range f sync 30 130 khz - capacitor on sst c sst 1nf - junction temperature t j ? 25 150 c- sync duty cycle dc 10 90 % - www.datasheet.co.kr datasheet pdf - http://www..net/
TDA16850-2 data sheet 18 04.01 4.3 characteristics note: the electrical characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range t a from ? 25 c to 85 c typical values represent the median values, which are related to production processes. if not otherwise stated, a supply voltage of v vcc = 15 v is assumed.. ) supply section vcc and vreg parameter symbol limit values unit test condition min. typ. max. zener voltage v z1 21 23 28 v i z1 =4ma, i opto =0 quiescent supply current i vcc or i vreg 5 6 9 ma gate disabled i opto =4ma 5 7 10 ma gate enabled i opto =4ma c l =0 supply current i vcc + i vreg 7 11 15 ma gate enabled i opto =4ma c l =4,7nf f sync = 100 khz standby regulation voltage via vreg v vreg 10 11 12 v v gate >2v switch drop voltage, sw1, from vreg to vcc, closed v sw1 -1,42,3v i sw1 = 8 ma v vreg = 10 v vreg input resistance, from vreg to gnd, sw1 opened r vreg 60 110 180 k ? off mode, threshold v vcc 6,5 7,5 8,5 v power up, rising voltage threshold, off mode to startup mode v vccup 19 21 24 v correlated to v z1 i opto = 120 a power up, threshold current, off mode to startup mode i vccup 30 100 170 a v vcc =v vccup ? 0,1v opto section parameter symbol limit values unit test condition min. typ. max. static opto current, threshold off mode to startup mode i opto dc ? 100 ? 50 ? 20 a v vcc = v vccup +0,5v opto current, pulswidth off mode to startup mode i opto puls 47,520 s i opto = 100 a v vcc = v vccup +0,5v opto current, threshold startup mode to normal mode i opto ? 2500 ? 2000 ? 1400 a opto current, threshold normal mode to standby mode and back i opto ? 2500 ? 2000 ? 1400 a opto current, threshold standby mode to power down mode and back i opto ? 240 ? 160 ? 70 a www.datasheet.co.kr datasheet pdf - http://www..net/
TDA16850-2 data sheet 19 04.01 opto current limit i opto -10,5 -8 -6,5 ma 0 v < v opto < 0,5v opto voltage v opto 122,5 v200 a < | i opto |< 5 ma opto current for duty cycle minimum i opto ? 2600 ? 2000 -1500 a opto current for duty cycle maximum i opto ? 6,6 ? 6 ? 5,4 ma correlated to duty cycle minimum oscillator section parameter symbol limit values unit test condition min. typ. max. standby mode, no sync signal f standby 15 20 25 khz - normal mode, no sync signal f normal 50 60 70 khz - oscillator frequency, line regulation ? f out -0,081 % ? v vcc =9v f = 60 khz sync section parameter symbol limit values unit test condition min. typ. max. sync threshold, voltage rising, leading edge triggered v sync 0,911,1v - sync threshold, hysteresis v sync 0,1 0,2 0,5 v - sync, input current i sync -540 a 0 v < v sync <2 v sync, negative clamp voltage v sync -1 ? = 0,7 -0,4 v i sync = ? 1 ma sync, positive clamp voltage v sync 2,5 3,5 5 v i sync = 1 ma min. sync range f sync 30 - 130 khz 130 khz - 200 khz max. sync range f sync 17 - 200 khz delay sync - gate t sync - gate 0,7 2,5 3,8 s f osc = 30 khz delay sync - gate t sync - gate 0,3 1,2 1,8 s f osc = 120 khz pwm section parameter symbol limit values unit test condition min. typ. max. cs input current i cs -5 ? 10 -20 a v cs = 1,35 v cs spike blanking sb cs -0,15- vs - sst softstart, charging current i 2 10 20 30 a- sst softstart, maximum voltage v ssmax 3 6 7,5 v correlated to power limitation opto section www.datasheet.co.kr datasheet pdf - http://www..net/
TDA16850-2 data sheet 20 04.01 sst voltage at power limitation max. v plimax 5,0 6,0 7,5 v f osc = 30 khz sst voltage at power limitation min. v plimin 3,0 3,8 4,6 v f osc = 120 khz gate section parameter symbol limit values unit test condition min. typ. max. gate low voltage v gate 0,50,851,2 v v vcc =2v i gate =5ma 0,7 1,0 1,5 v v vcc =2v i gate =20ma 0,05 0,25 0,35 v i gate =50ma ? 0,5 ? 0,25 -0,05 v i gate = ? 50 ma gate high voltage v gate 10 11 12 v v vcc =16v c l = 4,7 nf 89,710v v vcc =10v c l = 4,7 nf 789v v vcc = 9 v c l = 4,7 nf gate rise time t r 120 210 380 ns v gate = 2 v to 8 v c l =4,7nf 30 50 100 ns v gate =2v to 4.5v c l =4,7nf gate fall time t f 50 80 130 ns v gate = 9 v to 2 v c l =4,7nf gate current, peak, rising edge i gate ? 10,4 - a c l =4,7nf gate current, peak, falling edge i gate -1,22 a c l =4,7nf gate step voltage v gate 567v - gate charge q gate 150 nc f osc = 130 khz package p-dip-8 pwm section parameter symbol limit values unit test condition min. typ. max. www.datasheet.co.kr datasheet pdf - http://www..net/
TDA16850-2 data sheet 21 04.01 error section parameter symbol limit values unit test condition min. typ. max. cs slew rate minimum (mains undervoltage) sr cs 15 45 70 mv / s i opto = 4 ma f osc = 30 khz vcc threshhold voltage (ic supply overvoltage) v vccmax 21 23 28 v - temperature protection (ic overtemperature) t j 135 145 155 c- vreg min. voltage (vreg loop failure ) v vreg 2,3 3 3,3 v v sst > 2,6v vsst max. voltage (vreg loop failure ) v sst 2,0 2,6 3,1 v v vreg < 3v vcc threshhold voltage (ic supply undervoltage) v vccdwn 7,0 8.0 8,5 v - vcc protection mode discharging current i 1 10 13 20 ma v vcc = 11v sst protection mode discharging current i 3 12,54ma v sst = 5v delay time failure latch active t delay 30 70 110 s - cs threshold voltage (over current detection) v cs oc 1,1 1,2 1,3 v - sst discharge current, at over current detection i disc 1,5 3 4,5 ma v sst = 5v v cs = 2v cs threshold voltage (short circuit detection) v cs sc 1,35 1,5 1,65 v - www.datasheet.co.kr datasheet pdf - http://www..net/
TDA16850-2 data sheet 22 04.01 typ. max. duty cycle dependence on powerlimitation, frequency and cs slew rate (i opto = max) figure 17 v cs slew rate = 80 (mv/s) v cs slew rate = 100 (mv/s) v cs slew rate = 200 (mv/s) v cs slew rate = 300 (mv/s) f gate (khz) v cs max (mv) duty cycle (%) v cs max (mv) duty cycle (%) v cs max (mv) duty cycle (%) v cs max (mv) duty cycle (%) 30 910 36 930 28 1030 16 1170 13 60 580 46 600 38 770 23 870 18 120 390 59 400 57 550 36 670 29 0 200 400 600 800 1000 1200 1400 0 5 10 15 20 300mv/s 400mv/s 200mv/s 100mv/s 80mv/s 70mv/s 120khz 30khz 60kh z sec v cs mv t on www.datasheet.co.kr datasheet pdf - http://www..net/
TDA16850-2 data sheet 23 04.01 5 application circuits 5.1 application circuit 1. see description 5.3.1 figure 18 heater +5 v -20 v gnd ac 90v ~ 270v tle 4264 off sst vcc vreg sync gate opto cs vert. sync in out +12 v on/off suspend +80 v +190 v +20 v drv pwm power limit tda 16850 z1 5 1 3 6 4 2 7 8 oscillator overtemp. starting-up hysteresis power management 220nf 220nf www.datasheet.co.kr datasheet pdf - http://www..net/
TDA16850-2 data sheet 24 04.01 5.2 application circuit 2. see decription 5.3.2 figure 19 gnd c 90v ~ 270v hor. sync standby sst vcc vreg sync gat e opto cs +80 v +190 v +20 v -20 v heater in out +12 v on/off suspend +5 v tle 4264 drv pw m power limit tda 16850 z1 5 1 3 6 4 2 7 8 oscillator overtemp. starting -u p hysteresis power management 220nf 220nf www.datasheet.co.kr datasheet pdf - http://www..net/
TDA16850-2 data sheet 25 04.01 5.3 description of application circuits the application circuits shows two typical monitor power supplies with a wide input voltage range ( 90 - 230 v ac) and several outputs (+190 v, +80v, +20v, -20v, +12v, heater, +5v ). 5.3.1 application circuit 1 switch on via connector ? vert. sync ? . switch off via connector ? off ? . from off mode to startup mode via ? vert. sync ? . the power consumption in off mode is less then 1 watt. this application needs minimal external components. this application work with 20khz in startup and standby mode and 60 khz in normal mode provided by the internal oscillator. 5.3.2 application circuit 2 switch on and switch off via connector ? standby ? . no off mode. the 5 v output therefore is always on. switchover of tle 4264 input to 80 v winding automatically if the winding voltage becomes too low. in normal mode the oscialltor is synchronized via pin sync. published by infineon technologies ag st.-martin-strasse 53 d-81541 mnchen ? infineon technologies ag 2001 all rights reserved. attention please! t he information herein is given to describe certain components and shall not be considered as warranted characteristics. t erms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, des criptions and charts stated herein. infineon technologiesis an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologi es office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please cont act y our nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infin eon tech- nologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system , or to affect t he safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.datasheet.co.kr datasheet pdf - http://www..net/

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